HSINCHU, Taiwan — Silicon has a physical limit, and the world’s largest chipmaker is trying to see past it. TSMC, working with researchers from National Yang Ming Chiao Tung University, has demonstrated a transistor layer just 0.42 nanometers thick — a few atoms across — using an engineered interface that could point the way beyond silicon-based manufacturing.
The work, published in the journal Nature Electronics, tackles a problem that has stalled progress on atomically thin semiconductors. Transistors need an insulating layer, called the gate dielectric, that controls the flow of electrons. Making that layer thinner improves control but disturbs the delicate interface between materials, scattering electrons and erasing performance gains. Researchers have spent years trying to achieve thin dielectrics and strong performance at once; the TSMC-NYCU team found a way to get both.
Their approach was to rebuild the interface itself. The team placed an ultrathin layer of epitaxial aluminum onto a single-atom-thick semiconductor — molybdenum disulfide — then oxidized it to create an aluminum oxide layer about 0.42 nanometers thick, and added a hafnium oxide dielectric on top. The engineered interface serves two functions: it creates a smooth surface that lets the dielectric grow uniformly, and it acts as an atomic buffer that protects electron flow.
The result was transistors with an equivalent oxide thickness near one nanometer, low leakage, minimal hysteresis and a transconductance — a measure of how well a transistor converts input voltage into current — of 0.45 millisiemens per micrometer in devices with channels around 100 nanometers long. The combination of thin dielectric, strong electrical control and preserved carrier mobility is one researchers have sought for more than a decade.
The significance is in the materials. The transistors were built from monolayer molybdenum disulfide grown by chemical vapor deposition — the wafer-scale process that would be needed for real manufacturing — rather than the hand-exfoliated flakes that dominate academic research. That detail is what moves the work from laboratory curiosity toward something a foundry could eventually industrialize.
TSMC’s interest is strategic. The company’s conventional road map is crowded with demand: its N2 process entered volume production in late 2025 with dozens of tapeouts, and its A16 node with backside power delivery is set for production readiness in the second half of 2026. AI chips are consuming capacity as fast as the company can build it. But silicon’s scaling limits are approaching regardless of demand, and the industry’s leaders have been forced to bet on what comes next.
The 0.42-nanometer demonstration is a down payment on that future. Atomically thin semiconductors promise transistors that are smaller, faster and more energy-efficient than today’s silicon devices, and the interface problem has been the main obstacle between the promise and the product. By showing a manufacturable path to thin dielectrics on 2D materials, TSMC’s research arm is positioning the company to own the transition when it comes.
The transition will not come soon. Industry road maps still expect silicon to carry the load through the end of the decade, with nanosheet transistors, backside power and optical interconnects extending the existing platform. But the research pipeline matters: the company that controls the fundamental building blocks of the next materials generation will control the industry that follows, and TSMC has been methodically assembling that position.
The work also signals how the foundry industry’s competitive dynamics are shifting. Rivals are exploring their own post-silicon paths, and consortia in the U.S., Europe and Japan are funding 2D materials research. TSMC’s edge is scale: it can fund research, test at production scale and move results into fabs faster than academic teams or smaller competitors. The NYCU collaboration, with its wafer-scale focus, is a demonstration of that advantage.
For the engineers who build chips, the paper is a proof that the walls closing in on silicon have a door. The 0.42-nanometer layer is not a product; it is a route marker showing that the physics of the next generation is solvable with the right materials and the right interfaces. TSMC, which built its dominance on being first to every manufacturing transition of the past three decades, intends to be first to this one too.
The collaboration itself is notable. TSMC’s corporate research arm has long worked with Taiwanese universities, but the NYCU partnership shows how the company is using academic channels to explore risks that are decades from production. The paper’s authors include engineers from TSMC’s corporate research division alongside university faculty, a structure that lets the foundry steer fundamental research toward questions its process engineers actually care about — like whether 2D materials can be grown, patterned and packaged at the scales its fabs require.
The business context sharpens the stakes. TSMC’s customers — the designers of AI accelerators, phones and data-center chips — are all competing for the same scarce capacity, and the foundry’s pricing power has never been stronger. That revenue funds research with long horizons, including the post-silicon programs now gathering pace. Analysts said the economics of the current boom are effectively subsidizing the bets that will decide the next decade of the industry, and the 0.42-nanometer result is one of those bets paying early dividends in the lab.
The company’s posture, analysts said, is two-legged: run silicon as hard as it can go while building the escape route in parallel. The 2nm orders are full, the lab work is advancing, and the industry’s most valuable manufacturing franchise is betting that both legs hold — today’s demand paying for tomorrow’s materials.
