The message went out to suppliers in recent weeks: keep the development lines pointed at microbumps. TSMC, the world’s largest contract chipmaker, has decided to hold off on investing in hybrid bonding for high-bandwidth memory and is pushing instead toward mass production of finer microbumps, according to people familiar with the matter. Japanese and South Korean suppliers of materials and equipment have aligned their plans with the decision, and the microbump process is expected to enter volume production in the second half of 2028.
The choice settles, for now, one of the industry’s most closely watched technical questions. HBM, the specialized memory stacked beside artificial-intelligence accelerators, is the tightest link in the AI supply chain, and every major chipmaker’s road map bends around how much of it can be produced. TSMC does not make the memory itself, a business dominated by SK hynix, Samsung and Micron, but its advanced packaging increasingly decides how memory and accelerator meet, which gives the company an outsized voice in how the next generation is built.
Many in the industry expected that next generation, HBM4, to abandon microbumps for hybrid bonding, a technique that fuses copper directly to copper without solder and can raise interconnection density by as much as 15 times. The theoretical gains are real, but so are the obstacles: yields are punishing, the heat that builds inside a tall stack of fused dies is hard to manage, and the equipment needed to do the job at scale barely exists. JEDEC, the industry body that sets memory standards, has raised the maximum allowed stack height to 775 microns, and that extra headroom gave designers room to keep stacking tiers on the mature process. With the taller stacks permitted, HBM4 stays on microbumps, and hybrid bonding slips to HBM4E or HBM5.
TSMC’s decision is notable because the company is no stranger to the newer technique. It already uses hybrid bonding in SoIC, its platform for stacking logic chips, where the technology has proved itself in products such as the processors that package compute tiles side by side. Choosing a conservative route for HBM reflects a difference in terrain: logic stacking is TSMC’s own product, made on its own lines with its own yield learning, while HBM is built by memory makers who own the process and the risk. Jumping into an unproven joining technique on someone else’s product would concentrate exposure where TSMC has the least control.
The reasons are also commercial. Memory makers are expanding capacity as fast as they can, and a packaging change in the middle of that expansion would force them to rebuild production lines just as demand peaks. By keeping HBM4 on microbumps, TSMC lets the memory industry standardize the equipment and materials it is already ordering, and it buys time for hybrid bonding to mature before it must carry the industry’s highest-volume product.
For SK hynix and Samsung, the decision is close to a gift. Both companies have been racing to add capacity for customers such as Nvidia, which buys HBM in volumes measured in whole factories, and both have treated continuity in packaging as a competitive advantage over rivals who must learn new processes under pressure. The postponement means the capacity they are building now will not be made obsolete by a mid-cycle switch, analysts said, and the advanced-packaging arms race among the memory makers has been recalibrated around a process everyone already knows.
The market context makes the timing matter. AI accelerators ship with HBM measured in hundreds of gigabytes per system, and each new platform generation demands more memory and faster connections between the dies. Prices for HBM have stayed high enough that memory makers are selling every wafer they can produce, and the constraint on the industry has shifted from demand to manufacturing. In that environment, a packaging route that is proven, cheap and available now wins over one that is elegant but late.
Customers have their own reasons to welcome the delay. Nvidia and the other designers of AI accelerators care less about the elegance of the interconnect than about the supply of memory, and they have been pressing the memory industry to standardize on processes that scale quickly. A packaging switch that slowed HBM4 deliveries would have rippled through every server roadmap built around the new generation, so the conservative route is also the dependable one.
The postponement is not an abandonment. Bandwidth requirements will eventually outrun what solder joints can deliver, engineers say, and the suppliers aligned with TSMC are already developing hybrid-bonding materials for the generation after HBM4E, when stack heights and data rates will leave little choice. The question was never whether hybrid bonding would arrive, they argue, but which generation would carry it. TSMC’s answer pushes that day past 2028 and hands the next two years to the memory makers with the steadiest production lines and the most predictable costs.
