The chips that power the next generation of iPhones and Nvidia accelerators are about to get smaller. Taiwan Semiconductor Manufacturing Co., the world’s largest contract chip maker, is preparing to begin mass production of its 1.6-nanometer process — known internally as A16 — as early as the end of this year, according to people familiar with the matter, which would make it the first company in the world to ship chips on the node.
The timetable, reported on Aug. 20 and 21, puts TSMC ahead of its own earlier public guidance, which pointed to production readiness in the second half of 2026. A16 is the successor to the N2 process that TSMC is currently ramping, and it uses a technology the company calls Super Power Rail, which delivers power to chips from the back side of the wafer — a design change that improves performance and power efficiency at the cost of manufacturing complexity.
The significance is competitive as much as technical. TSMC’s leading-edge rivals are still working to master 2-nanometer production. Samsung Electronics, which has struggled to win high-volume orders for its advanced nodes, and Intel Corp., which has retreated from the leading edge under a cost-cutting program, are both at or behind the 2-nanometer level. If TSMC ships 1.6-nanometer chips by year-end, it will hold a full node of advantage over both.
That advantage compounds. Each node generation gives a chip designer roughly 15% to 20% better performance or power efficiency, and the customers who adopt the newest node first — Apple, Nvidia, AMD, Qualcomm — build products the market treats as the state of the art. TSMC’s position as the first and sometimes only supplier at the leading edge is the foundation of its pricing power and its near-90% share of the most advanced foundry business.
The A16 ramp is a test of TSMC’s ability to repeat a pattern it has managed for a decade: introducing a new node on schedule while the previous one is still generating record revenue. The company’s N3 family has been the workhorse of the AI boom, and its N2 line is in early production. A16 must prove out while demand for both continues, and the people familiar with the matter said TSMC’s fabs in Taiwan are already installing the equipment needed for pilot runs.
The customers are waiting. Apple is expected to be among the first to use A16 for its next-generation mobile processors, and Nvidia has reserved capacity for future accelerator generations built on the node, according to people familiar with the matter. The largest chip designers lock in capacity years ahead, and the queue for A16 started forming before the process was proven, a testament to how few alternatives exist at that frontier.
The technical hurdles are real. Back-side power delivery, the A16’s signature feature, requires a fundamentally different manufacturing flow — wafers must be processed, flipped and processed again — and yields at the introduction of a new node are notoriously difficult to control. TSMC has a history of making these transitions look smoother than they are, but the people familiar with the matter cautioned that the year-end target is an ambition, not a promise.
The geopolitical context adds a layer. TSMC is building fabs in Arizona and Japan as governments push to diversify chip production, but the most advanced process nodes have remained in Taiwan. A16 production will begin there, and the company’s technology roadmap is now a matter of national-security interest in Washington, Tokyo and Taipei. The U.S. Commerce Department has pressed TSMC to bring its most advanced nodes to Arizona, and the company has said its second Arizona fab will handle N2; whether A16 follows depends on demand and politics.
For the industry, TSMC’s lead has a double edge. Its customers benefit from access to the most advanced chips on earth; its competitors face a gap that grows with every node. Samsung and Intel have both said they plan to catch up — Samsung with its own 1.4-nanometer roadmap, Intel with a foundry strategy aimed at 2027 — but analysts said the economics argue against them: TSMC’s scale lets it amortize the billions of dollars a new node costs across more customers than anyone else can.
The margin math explains the scramble. A leading-edge foundry node costs on the order of $10 billion to develop, and the revenue required to justify it assumes volume no competitor currently has. TSMC’s customers underwrite its roadmap by paying premium prices for guaranteed capacity; Samsung and Intel are trying to build the same model from a smaller base, and each quarter that passes with TSMC ahead widens the gap.
The near-term question is whether the year-end target holds. TSMC executives have said publicly that A16 remains on schedule, and the company has never missed a node introduction by more than a few months. The people familiar with the matter said the first A16 wafers are expected to be qualified by the fourth quarter, with volume production ramping through 2027.
The longer-term question is what the node means for the AI buildout. The accelerators that power large language models are already supply-constrained, and each generation of chips adds capacity per wafer and cuts the cost per token. A16’s arrival, on top of the memory capacity now booked through 2028, would give the industry its next step of compute at a moment when every major lab is asking for more. The race to 1.6 nanometers is, in the end, a race to keep the AI boom supplied.
