The count was measured in wafers, and it took longer than the optimists predicted. Intel Foundry and ASML said Tuesday that High-NA EUV lithography equipment has now processed more than 1 million wafers cumulatively, with Intel’s usage exceeding that of every other chip maker combined. The figure gives the industry its first hard data point on a technology that cost billions to develop and years to bring into production.
High-NA EUV, short for high numerical aperture extreme ultraviolet lithography, is the industry’s most expensive bet on keeping Moore’s law alive. The machines, built by the Dutch equipment giant ASML, use a new optical system to project finer patterns onto silicon than the previous generation of EUV scanners can manage. Each system costs several times more than the equipment it replaces, and only a handful of companies in the world can afford to operate one.
Intel’s position in the story has been central from the start. The company took delivery of the first High-NA systems and committed to using them in production while rivals watched from the sidelines, accepting the risk of being first in exchange for a head start on the technology. On Tuesday that bet produced its first public return: Intel said its High-NA machines have processed more wafers than all other users combined, and it described the 1 million wafer mark as validation of its early commitment.
The two companies also announced they are working together on a change that could matter as much as the machines themselves: a larger reticle, the mask that carries the pattern printed onto silicon. The current format measures six by six inches; the new one extends to six by twelve. ASML and Intel said the larger format could improve productivity by roughly 40 percent, because a bigger mask means fewer exposures to print the same amount of circuitry.
The industry’s adoption curve is now visible in the announcements of the other two major customers. TSMC, the world’s largest contract chip maker, has confirmed it will introduce High-NA EUV around 2030, at its A10 and A11 technology generations, a timeline that lets it wait for the equipment and processes to mature before committing. Samsung has said it plans to use the technology in 2028, starting with memory rather than logic, an approach that reflects the different economics of its business.
The divergence in timing tells a story about how the semiconductor industry is coping with the end of easy scaling. TSMC’s decision to wait is not a rejection of High-NA; it is a calculation that the previous generation of EUV can carry it through the next several nodes, and that waiting lets ASML and Intel work out the bugs. Samsung’s plan to use the machines for memory first reflects the pressure DRAM makers face as their own scaling slows.
For Intel, the numbers matter beyond the technology itself. The company has been rebuilding its foundry business from a position of weakness, trying to convince customers that its factories can compete with TSMC, and its early lead in High-NA is one of the few areas where it can claim genuine advantage. The million-wafer figure is evidence that the machines work in production, not merely in development, and Intel executives have used every opportunity to remind the industry who took the risk.
Investors responded to the news Tuesday. Intel’s shares rose more than 7 percent in intraday trading, and several analysts raised their price targets, citing the company’s position in High-NA lithography as a reason to take the foundry turnaround more seriously. The stock’s move reflected relief as much as enthusiasm: after years of delays and cost overruns in Intel’s manufacturing plans, a concrete production result was welcome.
The economics of the High-NA buildout remain forbidding for the industry as a whole. Each machine costs hundreds of millions of euros, and the cleanrooms, power systems and trained staff needed to operate them add billions more per site. Only the largest chip makers can justify the investment, which is why the technology’s customer list has remained short even as its importance has grown. The million-wafer figure represents a small fraction of global production, but it is the beginning of the curve.
The next test will come as TSMC’s timeline approaches and Samsung’s memory plans take shape. If High-NA delivers the productivity gains ASML and Intel are claiming, the technology will become the industry’s standard by the early 2030s, and the companies that adopted it early will have amortized their investment across years of production. If the yields disappoint, the early adopters will have paid the price of being first with nothing to show but experience. Tuesday’s announcement makes the case that the experience is starting to pay.
