For two years, the race in AI semiconductors was about a single number: how many calculations a chip could perform per second. An analysis published in South Korea on September 27 argues the race has moved somewhere else entirely, to how quickly a chip can get its data out the door.
The bottleneck, the industry analysis found, has shifted from compute to data movement. A chip can only do useful work if memory and neighboring chips can feed it fast enough, and the copper wiring that has carried those signals for decades is running out of headroom. The proposed answer is co-packaged optics, or CPO: converting electrical signals into light right at the chip and sending them down fiber.
Samsung Electronics has put a timetable on the idea. The company is building silicon photonics technology and platforms, and plans to commercialize CPO in 2027 before beginning mass production in 2028 of products that combine AI semiconductors with silicon photonics.
Samsung has been circling the idea for years. As early as 2023 it proposed bringing optical interconnects inside high-bandwidth memory stacks, and in March it unveiled a foundry roadmap that would mass-produce silicon photonics technology starting in 2028. The new timetable extends that ambition to full CPO products a year earlier.
Samsung’s strategy is to sell the whole stack at once. It wants to bundle silicon photonics with its high-bandwidth memory, its system-semiconductor foundry and its advanced packaging into a single turnkey offer, betting that customers building AI systems would rather buy one integrated solution than assemble pieces from many suppliers.
SK Hynix is approaching the same problem from the memory side. Its researchers have published a roadmap for CPO in the journal Nature Electronics, arguing that linking memory and processors with optical connections could relieve the data-transfer bottlenecks that drag down large AI systems.
The paper, co-authored with researchers from American and Asian universities, quantifies the gap. Compute performance has roughly tripled every two years, while interconnect bandwidth has grown only about 1.4-fold over the same period, a mismatch the authors call the bandwidth wall.
The roadmap sets concrete targets. The authors describe systems with more than 100 terabits per second of bandwidth per node, energy use below one picojoule per bit, and chip-to-chip latency under ten nanoseconds, figures that would make optical links central to the largest training clusters rather than an add-on at their edges.
The ambition goes beyond faster links between chips. SK Hynix’s long-term architecture proposes a photonic interposer that would connect pools of processors and memory directly, letting multiple accelerators draw on shared memory rather than being limited to the memory sitting next to each one.
The two companies are chasing a market that barely exists yet but is growing quickly. IDTechEx, a British research firm, estimates the global CPO market is worth about $95 million this year, and that it will grow roughly 30 percent a year through 2035, surpassing $1.2 billion within a decade.
IDTechEx expects most of the early revenue to come from network switches rather than from the chips themselves, with each switch potentially packing more than a dozen CPO photonic circuits. Optical links for AI systems would make up roughly a fifth of the market, the firm estimates.
That is a small number by the standards of the semiconductor industry, which measures its largest markets in the tens of billions of dollars. But the forecast’s slope, not its size, is what has drawn the two Korean memory giants in.
The logic is simple. High-bandwidth memory is tightly packed around processors today because copper connections need to be short to stay fast. If optical links remove that distance constraint, memory can be pulled away from the chip, pooled, and shared, a change that would redraw how AI systems are built and who sells the key components.
For Samsung, the play is about vertical control. By combining silicon photonics with foundry, packaging and high-bandwidth memory, the company hopes to capture more of the value inside a single AI system rather than selling memory as one component among many.
For SK Hynix, the play is about staying relevant to the architecture. The company dominates high-bandwidth memory today, and its roadmap is a way to ensure that whatever replaces today’s tightly coupled designs keeps memory at the center rather than pushing it to the periphery.
The shift, if it materializes, would also rearrange the supply chain. Silicon photonics specialists such as Broadcom, Marvell and Coherent are positioned to benefit, while the memory makers try to keep high-bandwidth memory from being relegated to a commodity as the architecture around it changes.
Analysts said the two companies’ different approaches reflect different strengths. Samsung can point to a full manufacturing chain. SK Hynix can point to published research and deep ties to the system architects who will decide how next-generation clusters are assembled.
The transition will not happen quickly. Thermal management, manufacturing yield and reliability all remain unsolved at the scales the roadmaps describe, and copper will remain economical for short links for years.
What the September 27 analysis captured is the direction of travel. The industry spent two years adding more compute. The next competition will be about how fast that compute can talk, and the two companies that dominate memory are both betting the answer is light.
