Ahn Hyun opened his keynote at the SEDEX semiconductor exhibition in Seoul on Wednesday with a forecast that would have sounded like a sales pitch in a smaller room. The performance scale of AI infrastructure, he said, will grow roughly 20 times by 2030 compared with this year.
The president who oversees SK Hynix’s development operations put a number on the pace: an average annual increase of 109%. Three trends are expanding at once, he said, and they compound. The tasks models are asked to perform are getting more complex, each request carries more information, and the total number of inference requests keeps rising.
The consequence lands in the memory hierarchy. A model that answers in one pass needs little more than the weights it was trained on. An agent that holds a conversation, calls tools and returns to the same context dozens of times accumulates what engineers call a key-value cache, and that cache grows with every turn. It cannot all live in high-bandwidth memory, which is expensive and scarce. It cannot all sit in flash, which is slow to read. Mr. Ahn’s answer is to spread it deliberately across HBM, conventional DRAM and solid-state drives, and to bet the next generation on two technologies: DRAM stacked vertically in three dimensions, and a flash product known as High Bandwidth Flash, or HBF.
He is not selling the idea alone. The fastest memory available today is static random-access memory, and it is far too costly to deploy at the scale inference now demands, which is why the industry has spent a decade paying premiums for whatever holds the most data nearest the processor.
Hours later and a continent away, at the OCP Global Summit in San Francisco, SK Hynix put a product behind the forecast. Hoshik Kim, a senior vice president, introduced MARS, for Memory-Centric AI Rack-Scale System, a rack-level design that pulls memory out of individual servers and gathers it into a shared pool that compute nodes draw from as needed.
The problem it addresses is structural. In a conventional cluster, idle memory in one server cannot be lent to a busy neighbor, and adding capacity means buying an entire new node, so operators buy more graphics processors than the workload requires and pay for the excess in power and floor space. Pooling memory at rack scale, Mr. Kim said, moves the unit of planning from the server to the rack.
The measured gain came from an agentic inference service. By storing the cache generated across multi-turn conversations in the shared pool instead of exhausting graphics memory and local storage, time to first token improved three to five times over recomputing the context from scratch, the company said in its presentation, with the tail latency that governs user experience falling sharply.
The second bet is HBF, developed with SanDisk on a specification published through the Open Compute Project. It carries roughly half the bandwidth of HBM but about 14 times the capacity, Mr. Kim said, a trade that suits reading a long context once rather than holding a working set in place. Version 0.7 of the specification was released in July, version 1.0 is expected early next year, and SK Hynix plans to sample an HBF Cube early in 2028.
The open standard is deliberate, and it carries a cost. Publishing the interface through OCP, with support from Google and Tenstorrent among others, invites competitors to build compliant parts. SanDisk has already taped out its first HBF product, with samples targeted for 2027 and production in 2028, according to notes from analysts at Mizuho and Goldman Sachs who attended its investor day.
Both announcements land in a market that has been short of memory for the better part of two years, as data-center operators absorb whatever capacity the three suppliers can build. In a shortage, allocation becomes the industry’s most valuable currency, and scarcity is the commercial case for a capacity-heavy product such as HBF: it trades speed many workloads do not need for volume they cannot otherwise get.
SK Hynix brings an advantage to that contest. It held about 62% of HBM shipments in the second quarter of 2025 and roughly 57% of revenue by the third quarter, though Samsung has closed part of the gap, rising from 15% to 33% between the second quarter of 2025 and the same period this year.
What the company is proposing is a change in what it sells. A memory maker that ships parts competes on price, yield and allocation against three rivals. A memory maker that designs the rack in which those parts are pooled competes on architecture, and does so with the customers who buy its components as the counterparty in every design decision.
MARS is the harder sell precisely because it asks a great deal of buyers: a new unit of procurement, new software to schedule a shared pool, and trust that the pool performs under the tail latencies that decide whether an inference service is usable.
Mr. Ahn’s 20-fold figure assumes inference demand keeps arriving. If it does, the constraint that decides who wins the next decade of computing may not be the processor. It may be the shelf of memory behind it, and who decides how that shelf is arranged.
