TSMC decided this week to open the most technically demanding step of its CoWoS packaging process to outside contractors, a shift aimed at easing the biggest remaining bottleneck in AI chip supply, according to industry sources cited by South Korea’s Electronic Times. The move came as TSMC’s shares rose nearly 3% in pre-market trading, TradingKey reported.
For years, TSMC has licensed the back-end stage of the process, wafer-on-substrate, in which an interposer is bonded to the package substrate, to outsourced assembly and test firms such as ASE, Amkor and SPIL. The front-end step, chip-on-wafer, in which a processor and its high-bandwidth memory dies are attached to the interposer, was kept inside TSMC’s own fabs. That is the part now being opened up at scale, with ASE among the first partners, people familiar with the matter said.
The decision reflects the arithmetic of AI demand. Nvidia alone has reserved roughly 800,000 to 850,000 wafers of TSMC’s CoWoS capacity for 2026, more than half of the year’s total, according to estimates cited by TrendForce. Monthly capacity is projected to climb from about 70,000 wafers in 2025 to 130,000 to 140,000 by the end of this year, and still the supply-demand gap is expected to run around 20%. The process, developed more than a decade ago and first used for Nvidia’s GPUs, has become the standard way to build an AI accelerator.
The queues show why. Reported lead times for CoWoS packaging have stretched to 52 to 78 weeks, meaning an order placed today would not ship until well into 2028 on TSMC’s own lines. Chairman C.C. Wei told shareholders in June that this year’s planned production of AI accelerator chips using CoWoS was fully sold out, and he has repeatedly said TSMC welcomes partners willing to add packaging capacity. TSMC has doubled its advanced packaging output before, but each round of expansion takes new fabs and new equipment, and demand has kept running ahead.
Outsourcing the front-end step is a strategic concession. TSMC guards its high-margin packaging work because the process carries the highest technical difficulty and the tightest yield requirements in the packaging world, and it has outsourced only limited CoW volume in the past. Opening the door at scale transfers some production, and some yield responsibility, to partners who will now carry a piece of the risk. The payoff for TSMC is flexibility: outside capacity can come online faster than its own new fabs.
The ripple effects are already visible in the equipment industry. OSATs taking on CoW work are placing orders for new production lines, with demand concentrated in dicing tools for cutting wafers and interposers and bonding tools for joining them. South Korean suppliers including Hanmi Semiconductor, Avaco and Wonik are in purchase-order discussions for laser processing and bonding equipment, according to multiple industry sources, and the machines typically cost more than $1 million each.
The assemblers are spending accordingly. ASE raised its 2026 capital budget to a record $10.5 billion, and Amkor is expanding its U.S. operations, while JCET has budgeted $1.4 billion for AI packaging capacity. AMD has pushed ASE and SPIL to build their own chip-on-wafer lines rather than focusing only on back-end work, according to reports in June, a sign that chip designers want more than one path to packaged silicon.
TSMC’s calculus is that sharing the front-end beats losing the order. The company accounts for roughly 90% of global AI chip manufacturing, and its own packaging lines cannot scale fast enough to absorb demand from Nvidia and from cloud giants building custom chips. Handing volume to partners keeps the work inside the Taiwanese and allied packaging ecosystem rather than pushing it toward competitors such as Samsung, and it preserves TSMC’s pricing power on the steps it keeps.
Analysts cautioned that the move buys time more than it solves the problem. Adding qualified CoW capacity at outside firms takes quarters, and the 2026 gap of about 20% is expected to persist even with the outsourcing expansion. The real test, they said, will be lead times: if they start to narrow by next year, the strategy is working; if they keep stretching, TSMC will have to turn to more unusual measures.
The shift also changes the shape of the AI supply chain. Packaging, long treated as a commodity finishing step, now commands pricing power and investment that used to belong to the fabs alone. For Nvidia and the hyperscalers waiting on deliveries, the near-term effect is small, chips are still scarce. But the direction is clear: the industry’s tightest constraint is being attacked from both ends, with TSMC building in-house capacity, licensing more of its process know-how and handing volume to a growing group of partners that now share the burden of keeping AI chips flowing.
