The semiconductor industry’s scarcest commodity right now is not a new chip design. It is the memory that feeds the chips. In Seoul this week, AMD chief executive Lisa Su put the shortage in plain terms: memory supply is tight, and her company is working with customers to squeeze more out of every gigabyte they have.
Speaking to reporters in the South Korean capital, Su said AMD is collaborating closely with customers to optimize how much memory they use, and that deep cooperation across the memory supply chain is helping the company’s business keep growing. The framing is deliberate: for a chipmaker, the memory crunch is both a constraint and a competitive opening, and Su wants investors to see AMD managing it rather than being managed by it.
The pressure point is high-bandwidth memory, or HBM, the stacked DRAM that sits next to AI accelerators and moves data fast enough to keep them busy. Demand for HBM has run ahead of supply as companies race to build out AI computing, and the shortage has become one of the main limits on how quickly the accelerator market can grow.
Su described AMD’s HBM4 product in unusually warm terms. She said the company is very satisfied with HBM4 and that its progress is excellent, language that suggests the next generation of AMD’s AI chips will not be held back by memory availability or quality. The two South Korean memory makers, Samsung and SK Hynix, have given strong support, she said, and AMD expects the partnership to extend across several future product generations.
That pairing matters. Samsung and SK Hynix control the bulk of the world’s advanced memory production, and a chip designer’s relationship with them now determines how many accelerators it can ship. Su’s message to Seoul, delivered in the home market of both suppliers, was as much a signal to the memory industry as it was to investors.
She also made clear AMD is pushing its memory suppliers to expand capacity faster. For a company that does not make its own memory, the levers are limited: negotiate supply, help customers use less, and pressure suppliers to build more. Su’s comments suggest AMD is pulling all three at once.
The dynamic mirrors a broader squeeze across the AI supply chain. Chips, memory, power and data-center space are all in short supply in different degrees, and the companies that can secure them first are the ones that ship product. Memory has become an especially visible bottleneck because it sits between the two biggest spenders in the industry, the chip designers and the cloud operators that buy their accelerators.
Analysts said the memory shortage is likely to persist as long as AI capital spending keeps climbing. HBM capacity takes time to build, and the investment decisions Samsung and SK Hynix make now will shape supply for years. A designer like AMD can secure its own allotment through contracts and relationships, but it cannot will the fabs into existence.
For AMD, the stakes are clear. The company has positioned its Instinct line of AI accelerators as an alternative to Nvidia’s dominant chips, and its ability to win share depends in part on getting enough memory to ship every accelerator it can sell. A memory crunch that forces customers to ration their deployments would hit AMD harder than a rival with its own captive supply.
HBM is hard to make. The chips are stacked in layers and connected in ways that push the limits of packaging technology, and only a handful of companies can produce them at scale. Samsung and SK Hynix dominate, with Micron a distant third, and every major AI chip depends on their output. When demand for AI accelerators doubles, memory supply cannot double with it.
The imbalance puts AMD in a particular position. Nvidia, which sells the majority of AI accelerators, has locked in much of the available HBM supply through long-term agreements. AMD is further back in the queue, which is why Su is talking so directly about working with customers to use less memory and pressing suppliers to expand.
Su’s enthusiasm for HBM4 is significant because the product is the memory standard the next generation of accelerators will be built around. A chip designer that has secured HBM4 supply and validated the parts early can ship on schedule; one that has not will watch its road map slip. By saying HBM4 is progressing excellently, Su is telling investors that AMD’s next products are on track even as the broader market is rationing memory.
Su’s appearance in Seoul was, in effect, a visit to the source. The memory that will power AMD’s next generation of chips is being made a short drive from where she stood, and the message she carried was aimed at the companies building it.
For now, AMD’s bet is that the memory squeeze is a phase to be managed, not a wall to be hit. The company is signaling that supply for HBM4 is secured, customers are being coached to use less, and suppliers are being pushed to build more. Whether that is enough depends on how long the AI buildout keeps outpacing the fabs.
