The DRAM cell has been built the same way for four decades: one transistor, one capacitor, arranged flat on the same plane. The transistor is the switch. The capacitor is the bucket that holds the charge until something reads it, and it has to stay deep enough that the charge can still be detected before it leaks away. Every shrink of the cell shrinks the bucket, and the industry has stayed ahead of that problem by building the bucket taller, first as a trench cut into the silicon and later as a cylinder standing above it. That trick has an end, and the companies buying memory for AI systems can see it approaching.
The end is why a short report published on Nov 6 deserves more attention than its length suggests. According to two people with direct knowledge of the matter, TSMC has in recent weeks begun planning production of 3D DRAM, an advanced memory chip that stacks cells vertically instead of spreading them across the surface of a wafer. The request came from Nvidia, its largest customer. TSMC declined to comment.
If it proceeds, the pure-play foundry would make memory chips for the first time in its history. TSMC builds logic: the processors and accelerators that other companies design, on processes that take years and billions of dollars to bring up. It has never sold a DRAM die. The division of labor has held for a generation, with three companies, Samsung, SK Hynix and Micron, supplying nearly all of the world’s DRAM, and only Samsung operating a logic foundry of any size alongside its memory plants.
Nvidia’s interest is easy to trace and harder to satisfy. The accelerators it sells do not work without high-bandwidth memory, the stacked DRAM that sits beside the processor and feeds it at a rate ordinary memory cannot match. Each generation of accelerator carries more of it, and each stack consumes far more wafer area per bit than the DRAM in a laptop, because the dies are thinned, stacked and tested before packaging. Demand for AI hardware now competes directly with demand for the memory inside phones, cars and servers, and the shortage that results shows up as a line item in every accelerator’s bill of materials.
3D DRAM is not the same product as the memory in those stacks. High-bandwidth memory is largely a packaging problem: it puts DRAM close to the processor and widens the connection between them. 3D DRAM is a density problem: it puts more cells into the same footprint so a wafer yields more bits. The engineering challenges differ, and both draw on the same constrained supply of DRAM wafers. A process that raises bits per wafer would ease the shortage at its source, which is the reason a request from Nvidia would carry weight with a foundry that has spent its existence turning wafer area into transistors.
A process would be the smallest part of what TSMC needs. DRAM manufacturing runs on different equipment and different materials from logic. The capacitor requires high-aspect-ratio etching and deposition steps that logic fabs do not perform at volume, and yields improve along a learning curve the three incumbents have been climbing for decades. TSMC has the process engineering staff to attempt it. It does not have the recipes, the customer relationships in memory, or the pricing power that comes from selling a standardized part into a market with three sellers.
The business model is the harder mismatch. TSMC builds capacity against commitments from named customers, and its margin comes from charging for a service few competitors can provide. Memory is a commodity whose price resets every quarter and whose history is a sequence of shortages and gluts. A foundry that added memory capacity for one customer would be adding a business where the buyer’s willingness to pay collapses exactly when the capacity arrives, which is what happened to every memory maker in 2018 and again in 2022.
There is a second-order effect that runs the other way. Nvidia already relies on TSMC for its logic and on a handful of suppliers for its memory stacks. Asking its foundry to become a memory supplier would concentrate more of its supply chain inside one company, and would give that company a view of both halves of the cost of an accelerator. For TSMC the appeal is the same fact seen from the other side: the customer that defines demand for AI silicon is asking it to own a larger share of the bill of materials.
The incumbents would not be passive. Samsung and SK Hynix have spent two years converting capacity to high-bandwidth memory because that is where the margin sits, and both have their own vertical DRAM work under way. A foundry arriving in the field would bring better process control and a customer that sets the specification, which is roughly the position TSMC occupied in logic when it took the market from the integrated manufacturers two decades ago. The difference is that logic rewarded the best process, while memory rewards whoever adds capacity at the right moment.
None of this is a plan yet. Planning production and committing capital are separate decisions, and the second is answered by contracts rather than by reports. The number to watch is not the disclosure but the equipment order, because a 3D DRAM line requires tools TSMC does not currently buy in volume. Until that order appears, the report describes an evaluation, and the useful question is what Nvidia would have to guarantee to turn an evaluation into a commitment measured in billions.
