The number that best describes the packaging bottleneck is a multiple of the reticle, the largest field a lithography tool can expose in a single pass. TSMC’s CoWoS-L interposer is in mass production at 5.5 times that size. The company’s roadmap takes it to 14 times by 2028, and larger still in 2029.
Each step in that sequence is an engineering problem. Increasingly, it is also a pricing one. Supply-chain sources said Oct. 27 that TSMC and its assembly and test partners are evaluating a new round of CoWoS price increases of 10% to 20%. Separately, TSMC has settled on raising wafer prices by 3% to 6% by process node from January 2027, with 2-nanometer and 3-nanometer among the steepest increases.
The cause is arithmetic. Accelerator dies keep growing, and the number of high-bandwidth memory stacks bonded around them keeps rising. Every additional stack widens the interposer, and a wider interposer reduces how many units fit on a panel, on a tool, and in a month of output. The package, not the transistor, has become the unit of scarcity.
That has consequences for the whole supply chain. Equipment lead times for packaging tools have stretched from three to six months to six to eight, according to the same supply-chain accounts, and customers have responded by prioritizing locked delivery slots over price negotiations. When a buyer stops haggling, it is telling you what it expects capacity to look like next year.
The second wall is test. Nvidia’s Blackwell generation takes roughly four times as long in final test as Hopper did, and the Rubin generation may reach seven times. Test time is not a fixed cost that can be amortized away; it consumes tool hours in direct proportion to complexity, and it has become the stage where schedules quietly slip.
Forecasts circulating among institutional analysts put CoWoS monthly capacity above 130,000 wafers in 2026 and at 200,000 in 2027. Those are large numbers by the standards of two years ago, when advanced packaging was a niche line item inside a foundry’s revenue table. They are also, by the reckoning of the buyers placing orders, not large enough.
The pricing power on display is unusual for the foundry business. TSMC has historically raised wafer prices at node transitions, when a new process justifies a new rate card. It has rarely been able to reprice a mature packaging service mid-cycle. The current negotiation is different in kind: the constraint is physical, the demand is contracted years ahead, and the alternatives are scarce enough that a 20% increase is a smaller problem than a missed shipment.
Who absorbs the increase is the open question. Accelerator makers will try to pass it to cloud operators, who will try to pass it to customers of compute, who in most cases have already signed multiyear agreements at fixed rates. Somewhere in that chain a margin compresses. Analysts said the packaging line item is small enough relative to total system cost that the increase is unlikely to change purchasing decisions, which is another way of saying the buyer has no choice.
Memory is the other half of the squeeze. More HBM stacks per package means more silicon per accelerator and more of the packaging area consumed by memory that does no computing. The economics of an AI rack are increasingly driven by how much of the interposer is spent on memory rather than logic, and by how efficiently that memory can be cooled and powered.
The risk in all of this is timing. Capacity added for a 2026 shortage can arrive into a 2028 surplus, and packaging lines are among the least flexible assets in the industry: once built, they have to be fed. If AI infrastructure spending growth decelerates, the same scarcity that supports a 20% increase becomes a fixed cost with no pricing power behind it. Foundry executives have lived through that pattern in memory and in mature-node logic.
For now the direction is one way. Reticle multiples rise, stack counts rise, test times rise, and every one of those variables pushes cost per accelerator up at a moment when buyers are committing to gigawatt-scale deployments. TSMC’s customers have spent two years securing wafer starts. They are now discovering that the wafer was never the last constraint in the chain.
The 2027 wafer increase is the more consequential number in the long run, because it applies across the product line and it is already decided rather than under review. Three to six percent sounds modest against a 20% packaging increase. Applied to every advanced node shipment for every customer, it is the larger sum.
What the negotiations reveal is where the industry’s real bottleneck has moved. For a decade the question was who could get the most advanced lithography. The question now is who can bond the most memory to the largest piece of silicon and still test it in a commercially useful amount of time. The answer, for the moment, is one company, and it is repricing accordingly.
